1. Field of the Invention
The present invention relates to a system and a method for regenerating a stable clock signal for a semi-synchronization type digital demodulating apparatus used in satellite communication, and more particularly to the system and the method for regenerating the stable clock signal with a reduced jitter component.
2. Description of the Related Art
There have conventionally been proposed the above-mentioned type of various clock-signal regenerating systems for use in a semi-synchronization type digital demodulating apparatus. Of these, such a system is known that over-samples a change point in demodulated analog data using an analog/digital (A/D) converter and then adjusts that data""s sampling timing using a PLL (Phase Lock Loop).
Note here that throughout the following drawings, same components are indicated by same reference symbols and numerals. As shown in FIG. 3, at an input terminal 1 to which is input an demodulated analog data signal with a symbol frequency Fs, an A/D converter 2 is connected, which converts the demodulated analog data signal into a digital signal.
To the A/D converter 2 is connected a voltage-controlled oscillator (VCXO) 8, which outputs a clock signal 12 having a sampling frequency (2* Fs) twice as high as the symbol frequency (Fs) to the A/D converter 2.
The A/D converter 2 is in turn connected to a data-change-direction detecting circuit 3, which receives a most significant bit (MSB) converted at the AID converter 2 to detect a data-change direction of the above-mentioned demodulated analog data and then output a data-change-direction signal 13. Since information of the data-change direction is enough to tell whether the demodulated analog data changed from +1xe2x86x92xe2x88x921 or xe2x88x921xe2x86x92+1 in direction, not all bits but only a most significant bit is required to make a decision of that direction.
The A/D converter 2 is also connected to a phase-difference detecting circuit 4, which detects a phase difference between a clock signal 12 of the voltage-controlled oscillator 8 and demodulated analog data at the input terminal 1, and outputs a phase-difference signal 14.
To the data-change-direction detecting circuit 3 and the phase-difference detecting circuit 4 is connected a multiplier (XOR) 5, which multiplies the phase-difference signal 14 from the phase-difference detecting circuit 4 by the data-change-direction signal 13 from the data-change-direction detecting circuit 3, and outputs a resultant phase-difference signal including information of phase lag and lead.
To the multiplier 5 is connected a digital/analog (D/A) converter 6, which converts a digital output signal from the multiplier 5 into an analog signal.
To the D/A converter 6 is connected a low-pass filter (LPF) 7, which removes a high-frequency component from an output signal of the D/A converter 6 and outputs the resultant phase control signal to the voltage-controlled oscillator 8, to control the voltage-controlled oscillator 8 so as to synchronize in phase the above-mentioned demodulated analog data with the clock signal 12.
To the voltage-controlled oscillator 8 is connected a frequency divider 9, which divides to xc2xd the frequency of a signal obtained by thus phase-synchronizing the above-mentioned demodulated analog data and the clock signal 12 and then output thus regenerated clock signal at an output terminal 10.
As shown at the upper part of FIG. 4, the demodulated analog data is input at the input terminal 1, to form an eye pattern which is the analog signal with the frequency Fs and also which changes in amplitude between two peak positions of xe2x80x9c+1xe2x80x9d and xe2x80x9cxe2x88x921.xe2x80x9d
As shown at a lower part of the FIG. 3, the clock signal 12 sent from the voltage-controlled oscillator 8 to the A/D converter 2 has, as mentioned above, a sampling frequency of 2* Fs, so that double over-sampling is performed at the A/D converter 2.
At the A/D converter 2, as shown in the FIG. 3, data is sampled at two points, on a rising edge of the clock signal 12, of one data convergence point of timing A and an other data convergence point (zero-crossing point) of timing B. That is, the timing A is a peak position of the demodulated analog data and the timing B, the zero-crossing point thereof.
Next, an example of operations of the data-change-direction detecting circuit 3 is explained as follows. The data-change-direction detecting circuit 3 uses only the MSB of the demodulated analog data sampled by the A/D converter 2 and also the data present at the sampling timing A shown in FIG. 4, to detect the data-change direction.
That is, although the MSBs of the demodulated analog data sampled at the timing points A and B shown in FIG. 4 are input to the data-change-direction detecting circuit 3, it can detect the data-change direction using only the demodulated analog data that was sampled at the timing A.
Since a center voltage (DC offset voltage) of the demodulated analog data input to the A/D converter 2 is aligned with a center of an input range for the A/D converter 2, peak positions xe2x80x9c+1xe2x80x9d and xe2x80x9cxe2x88x921xe2x80x9d of the demodulated analog data can be decided using only the MSB of the data sampled at the timing A.
The data-change-direction detecting circuit 3 uses two consecutive data pieces sampled at the timing A shown in FIG. 4, to detect a change in the peak position of the demodulated analog data from xe2x80x9c+1xe2x80x9d to xe2x80x9cxe2x88x921xe2x80x9d or vice versa. For example, the data-change-direction detecting data-change-direction detecting circuit 3 compares the MSB of the data sampled at t=1 to that at t=3, then that at t=3 to that at t=5, and then that at t=5 to that at t=7, and so on, respectively.
When the data-change-direction detecting circuit 3 decides, based on this comparison, that the demodulated analog data changed from its peak positions of xe2x80x9cxe2x88x921xe2x80x9d to xe2x80x9c+1,xe2x80x9d it outputs xe2x80x9c+1xe2x80x9d as the data-change direction signal 13. When the data-change-direction detecting circuit 3 decides a change of the demodulated analog data from its peak positions xe2x80x9c+1xe2x80x9d to xe2x80x9cxe2x88x921,xe2x80x9d it outputs xe2x80x9cxe2x88x921xe2x80x9d as the data-change direction signal 13.
If the demodulated analog data stays unchanged, for example, as from xe2x80x9cxe2x88x921xe2x80x9d to xe2x80x9cxe2x88x921xe2x80x9d or from xe2x80x9c+1xe2x80x9d to xe2x80x9c+1,xe2x80x9d the data-change-direction detecting circuit 3 outputs xe2x80x9c0xe2x80x9d as the data-change-direction signal 13.
Next, an example of operations of the phase-difference detecting circuit 4 is described as follows. The phase-difference detecting circuit 4 in turn receives demodulated analog data sampled at the timing points A and B, of which the data sampled at the timing B is used to detect the phase difference between the clock signal 12 and the demodulated analog data as follows.
When, as shown in FIG. 5A, demodulated analog data is changed in its peak position from xe2x80x9cxe2x88x921xe2x80x9d to xe2x80x9c+1,xe2x80x9d changes in the demodulated analog data of waveforms (24-1), (24-2), and (24-3) indicate a state where phase synchronization is established between the clock signal 12 and the demodulated analog data, while changes of the demodulated analog data of waveforms (24-4) and (24-5) indicate the state where that synchronization is not established therebetween.
Likewise, as shown in FIG. 5B, when demodulated analog data changed in its peak position from xe2x80x9c+1xe2x80x9d to xe2x80x9cxe2x88x921,xe2x80x9d changes in the demodulated analog data of waveforms (25-1), (25-2), and (25-3) indicate the state where phase synchronization is established between the clock signal 12 and the demodulated analog data, while changes in the demodulated analog data of waveforms (25-4) and (25-5) indicate the state where synchronization is not established therebetween.
As shown in FIG. 5A, the prior-art phase-difference detecting circuit 4 detects, with respect to the zero-crossing position, the phase difference of xc2x1xcex94V1 for the change of the demodulated analog data of the waveforms (24-1) and (24-3) and that of xc2x1xcex94V2 (xcex94V2 greater than xcex94V1) for a change of the demodulated analog data of the waveforms (24-4) and (24-5).
Moreover, as shown in FIG. 5B, the prior-art phase-difference detecting circuit 4 detects, with respect to the zero-crossing position, the phase difference of xc2x1xcex94V1 for the change in the demodulated analog data of waveforms (25-1) and (25-3) and that of xc2x1xcex94V2 for the change of the demodulated analog data of waveforms (25-4) and (25-5).
Conventionally, these phase differences of xc2x1xcex94V1 and xc2x1xcex94V2 have been used for feedback in a loop formed by the multiplier 5, the D/A converter 6, the low-pass filter 7, and the voltage-controlled oscillator 8.
Note here that it is appropriate to use the phase difference of xc2x1xcex94V2 for the above-mentioned changes of the demodulated analog data of the waveforms (24-4) and (24-5) and those of the demodulated analog data of the waveforms (25-4) and (25-5), because that demodulated analog data actually has the phase shift as against the clock signal 12. However, it is not appropriate to use the phase difference xc2x1xcex94V1 for the above-mentioned changes of the demodulated analog data of the waveforms (24-1) and (24-3) and those of the demodulated analog data of the waveforms (25-1) and (25-3), because that demodulated analog data actually has no phase shift as against the clock signal 12.
This is because that if the phase difference of xc2x1xcex94V1 is used for the changes of the demodulated analog data of the waveforms (24-1) and (24-3) or those of the waveforms (25-1) and (25-3), it may cause the clock signal 12 to jitter.
To remove this jitter, the low-pass filter 7 must have a reduced band width. If the band width of the low-pass filter is reduced, however, fluctuations in original phase difference cannot accurately be tracked, thus leading to a problem that regeneration accuracy of the clock signal 12 cannot be improved.
In view of the above, it is an object of the present invention to provide a regeneration system and a method capable of removing causes of jitter occurrence and, at a same time, accurately tracking fluctuations in phase difference, thus improving accuracy of clock signal regeneration.
According to a first aspect of the present invention, there is provided a clock signal regenerating system for regenerating a clock signal by feeding back a phase difference between a demodulated analog data signal and the clock signal, including:
an analog/digital converter for using the clock signal to over-sample the demodulated analog data signal, thus converting the demodulated analog data signal into a digital signal;
a data-change-direction detecting circuit for using a change in data of the demodulated analog data signal sampled at a peak position thereof by the analog/digital converter using the clock signal, to detect whether a data-change direction of the demodulated analog data signal is in an ascending direction or a descending direction;
a threshold selecting circuit for holding a threshold and also deciding whether the data of the demodulated analog data signal sampled at a zero-crossing position thereof by the analog/digital converter using the clock signal is of a positive or negative value, thereby selecting the threshold;
a phase-difference detecting circuit for comparing the data of the demodulated analog data signal sampled at the zero-crossing position thereof by the analog/digital converter using the clock signal and the threshold selected by the threshold selecting circuit, to detect data sampled in excess of the threshold as a phase difference; and
a multiplier for multiplying data of a phase-difference detected by the phase-difference detecting circuit by data in the data-change direction detected by the data-change-direction detecting circuit, to feed back a resultant phase difference.
With the foregoing first aspect, only when a phase shift actually occurs between demodulated analog data and the clock signal, the phase difference is detected and fed back, to prevent a jitter from occurring to the clock signal in order to enhance accuracy of the regenerated clock signal and also largely exceed a feedback loop filter""s frequency band, thus improving tracking performance against fluctuations in the phase.
In the foregoing aspect, a preferable mode is one wherein the above-mentioned analog/digital converter uses versus the above-mentioned demodulated analog data signal the clock signal having a sampling frequency twice as high as a symbol frequency, to enable sampling the demodulated analog data signal at its peak and zero-crossing positions.
That is, each time the demodulated analog data is sampled using the clock signal, the data sampled at the alternating peak and zero-crossing positions is used to enable detecting of the change in direction of the demodulated analog data, selecting of the threshold, and detecting of the phase difference.
Also, a preferable mode is one wherein, based on MSB of the demodulated analog data, the data-change-direction detecting circuit detects the data-change direction, thus permitting the threshold selecting circuit to select the threshold.
That is, since the threshold is selected depending on whether the data sampled at the zero-crossing position is lager than 0 or not, it is sufficient only to use the MSB in selection.
Furthermore, a preferable mode is one wherein, when the sampled data changes from its peak positions xe2x80x9cxe2x88x921xe2x80x9d to xe2x80x9c+1,xe2x80x9d the data-change-direction detecting circuit selects xe2x80x9c+1xe2x80x9d as the data-change direction and; when that sampled data changed from its peak positions xe2x80x9c+1xe2x80x9d to xe2x80x9cxe2x88x921,xe2x80x9d the data-change-direction detecting circuit selects xe2x80x9cxe2x88x921xe2x80x9d as the data-change direction and the threshold selecting circuit holds xc2x1xcex94Vth as the threshold in such a manner that when the data sampled at the zero-crossing position is positive, it selects a threshold +Vth and, if it is negative, selects a threshold xe2x88x92Vth; and when the data sampled at the zero-crossing position is not larger than the threshold +Vth and not smaller than the threshold xe2x88x92Vth, the phase-difference detecting circuit sets the phase difference to 0 and, if the data sampled at the zero-crossing position is larger than the threshold +Vth or smaller than the threshold xe2x88x92Vth, sets the data sampled at the zero-crossing position to the phase difference.
Thus, based on the data-change direction signal obtained by detecting the data-change direction and the positive/negative thresholds selected according to the positive/negative value of the data sampled at the zero-crossing position, the phase difference actually present between the demodulated analog data and the clock signal can be detected and used in feedback.
Furthermore, a preferable mode is one wherein, the data-change-direction detecting circuit sets the data change direction to xe2x80x9c0xe2x80x9d if the sampled data stayed unchanged as from peak positions xe2x80x9c+1xe2x80x9d to xe2x80x9c+1xe2x80x9d or from peak positions xe2x80x9cxe2x88x921xe2x80x9d to xe2x80x9cxe2x88x921xe2x80x9d.
In such a manner, if no phase shift is detected between the demodulated analog data and the clock signal, no phase difference is fed back.
Also, a preferable mode is one wherein, the threshold selecting circuit selects a threshold 0 when synchronization with the clock signal is established and, after that establishment, selects the threshold +Vth or xe2x88x92Vth.
With this mode, when synchronization is established as mentioned above, priority is given to capture and, after that establishment, priority is given to improvement in accuracy of clock signal regeneration.
Also, according to a second aspect of the present invention, there is provided a method for regenerating a clock signal by feeding back a phase difference between demodulated analog data signal and the clock signal, including the steps of:
over-sampling the demodulated analog data signal using the clock signal, thus converting the demodulated analog data signal into a digital signal;
deciding a change in data of the demodulated analog data signal sampled at a peak position thereof by the clock signal, to detect whether the demodulated analog data signal changed in an ascending direction or a descending direction;
holding a threshold and also deciding a positive/negative sign of data of the demodulated analog data signal sampled at a zero-crossing position thereof using the clock signal, to select the threshold;
comparing the data of the demodulated analog data signal sampled at the zero-crossing position by the clock signal and a set threshold, to detect data sampled in excess of the threshold as the phase difference; and
multiplying data of a detected phase difference by data in detected data-change direction, to feed back a resultant phase difference.
With the foregoing second aspect, it is possible to prevent the clock signal from jittering and to enlarge a band width of a feedback loop filter, in order to provide accurate tracking of fluctuations in phase difference, thus improving accuracy of the regenerated clock signal.